The invention relates to porous polyurethane polishing pads useful for polishing at least one of magnetic, optical and semiconductor substrates. For example, the polishing pads are particularly useful for chemical mechanical polishing (CMP) of semiconductor wafer materials and, more particularly, to low-defect methods for polishing semiconductor substrates.
The production of semiconductors typically involves several chemical mechanical polishing (CMP) processes. In each CMP process, a polishing pad in combination with a polishing solution, such as an abrasive-containing polishing slurry or an abrasive-free reactive liquid, removes excess material in a manner that planarizes or maintains flatness for receipt of a subsequent layer. The stacking of these layers combines in a manner that forms an integrated circuit. The fabrication of these semiconductor devices continues to become more complex due to requirements for devices with higher operating speeds, lower leakage currents and reduced power consumption. In terms of device architecture, this translates to finer feature geometries and increased numbers of metallization levels. These increasingly stringent device design requirements are driving the adoption of smaller and smaller line spacing with a corresponding increase in pattern density. The devices' smaller scale and increased complexity have led to greater demands on CMP consumables, such as polishing pads and polishing solutions. In addition, as integrated circuits' feature sizes decrease, CMP-induced defectivity, such as, scratching becomes a greater issue. Furthermore, integrated circuits' decreasing film thickness requires improvements in defectivity while simultaneously providing acceptable topography to a wafer substrate; these topography requirements demand increasingly stringent planarity, line dishing and small feature array erosion polishing specifications. Furthermore higher polishing removal rates are required to improve wafer throughput and, since both metal and dielectric materials are being polished simultaneously, the relative removal rates of metal to dielectric materials are important. In order to satisfy future wafer integration needs, higher dielectric (e.g. TEOS) to metal (e.g. copper) removal rate selectivity ratios are required.
Historically, cast polyurethane polishing pads have provided the mechanical integrity and chemical resistance for most polishing operations used to fabricate integrated circuits. For example, polyurethane polishing pads have sufficient tensile strength and elongation for resisting tearing; abrasion resistance for avoiding wear problems during polishing; and stability for resisting attack by strong acidic and strong caustic polishing solutions. The IC1000™ polishing pad supplied by Dow Electronic Materials represents the industry standard polyurethane polishing pad suitable for polishing multiple substrates, such as aluminum, barrier materials, dielectrics, copper, hard masks, low-k dielectric, tungsten and ultra low-k dielectrics (IC1000 is a trademark of Dow Electronic Materials or its affiliates.).
Over the last several years, semiconductor manufacturers have been moving increasingly to poromeric polishing pads, such as Politex™ polyurethane pads for finishing or final polishing operations in which low defectivity is a more important requirement (Politex is a trademark of Dow Electronic Materials or its affiliates.). For purposes of this specification the term poromeric refers to porous polyurethane polishing pads produced from aqueous or non-aqueous solutions. The advantage of these polishing pads is that they provide efficient removal with low defectivity. This decrease in defectivity can result in a dramatic wafer yield increase.
A polishing application of particular importance is copper-barrier polishing in which low defectivity is required in combination with the ability to remove both copper and TEOS dielectric simultaneously, such that the TEOS removal rate is higher than the copper removal rate to satisfy advanced wafer integration designs. Commercial pads such as Politex polishing pads do not deliver sufficiently low defectivity for future designs nor is the TEOS:Cu selectivity ratio high enough. Other commercial pads contain surfactants that leach during polishing to produce excessive amounts of foam that disrupts polishing. Furthermore, the surfactants may contain alkali metals that can poison the dielectric and reduce the semiconductor's functional performance.
Despite the low TEOS removal rate associated with poromeric polishing pads, some advanced polishing applications are moving toward all-poromeric pad CMP polishing operations because of the potential of achieving lower defectivity with poromeric pads versus other pad types such as IC1000 polishing pads. Although these operations provide low defects, the challenges remain to further decrease pad-induced defects and to increase polishing rate.